1. Field of the invention
The present invention relates to the field of memory accessing, and more particularly to accessing contiguous memory with a limited number of address bits.
2. Prior art
In accessing memory, a variety of prior art techniques are known, wherein address signals from a processor accesses the memory. In some instances, a limited address space is available to access the memory, which memory has a greater capacity than that defined by the address space. That is, for a given size memory, an adequate number of address bits are not available to access the full extent of the memory. One technique of addressing a memory which has greater capacity than that defined by the address space is the use of bank switching. In bank switching, a limited address space is used to address two or more banks of memory, wherein the processor under program control selects an appropriate bank, such as by activating one memory bank while the other bank(s) is kept inactive.
In a second tecnique, an alternate addressing mode is used, wherein signals on data lines are also used to select a portion of the memory. For example, in U.S. Pat. No. 4,685,084 an alternate page mode addressing scheme is described wherein data bits are used to select the appropriate page when in the alternate addressing mode. However, the alternate addressing scheme utilizing page mode, which is taught in U.S. Pat. No. 4,685,084, is typically used for memory space in a single MOS integrated circuit (IC) memory and is used for the purpose of dividing the memory into various pages. However, as memory size increases another level of memory accessing hierarchy is needed. In the event multiple memory arrays are used, or alternatively, multiple memory devices (in the way of multiple memory chips) are utilized, another hierarchical scheme which is one level above the page mode scheme is needed. Further, it would be advantageous to provide the additional memory by having pin compatibility to existing memory devices. For example, it would be advantageous to take a megabit (Mbit) memory device, such as a 1Mbit erasable programmable read-only memory (EPROM), to provide a pin-compatible four 1Mbit EPROM chip set, wherein this 4 Mbit memory space is accessed by the address space of the 1 Mbit scheme.